The RX3i CPU is designed for real-time control of machines, industrial processes, and material handling systems. The CPU communicates with programming software and HMI devices via serial communication using the SNP Slave protocol.

It interfaces with I/O and Intelligent Option modules through a dual backplane bus architecture that provides:

High-speed PCI backplane for fast data throughput with advanced I/O modules

Serial backplane that enables easy migration of existing Series 90-30 I/O

This dual-bus design protects legacy investments while enabling high-performance system expansion.

Features
Memory and Data Handling

10 MB battery-backed user memory

10 MB non-volatile flash user memory

Access to bulk memory using %W reference tables

Configurable data and program memory

Supports bit-in-word referencing, allowing individual bits within a WORD reference in retentive memory to be used as Boolean inputs and outputs in logic, function blocks, and calls that accept bit parameters

Programming and Application Support

Supports programming in:

Ladder Diagram (LD)

Structured Text (ST)

Function Block Diagram (FBD)

Supports auto-located symbolic variables with unrestricted use of user memory

Supports up to 512 program blocks, with a maximum block size of 128 KB

In-system upgradeable firmware

I/O and System Compatibility

Reference table sizes include:

32 Kbits for discrete %I and %Q

Up to 32 Kwords each for analog %AI and %AQ

Compatible with most Series 90-30 modules and RX3i expansion racks
(For supported I/O, communications, motion, and intelligent modules, refer to the PACSystems RX3i Hardware and Installation Manual, GFK-2314.)

Communications and Time Synchronization

Two integrated serial ports:

RS-485

RS-232